1. Field of the Invention
The invention relates to the field of computer communication. More particularly, the invention relates to an apparatus and method for buffering data in a communication system.
2. Description of the Related Art
Referring to FIG. 1, a buffering arrangement 12 can typically be provided between a media access control (MAC) interface logic circuit and a physical interface unit 14 in a communication system, in which the MAC logic circuit (not shown) is incorporated in control logic 10. The buffering arrangement 12 is useful for buffering a stream of data between a local bus 100 and the physical interface unit 14 which are not synchronized. For example, the local bus 100 is a 32-bit PCI bus supporting 132 Mbytes/second peak transfer rate and the physical interface unit 14 interfaces with the commonly-used 10 or 100 Mbps Ethernet. In FIG. 1, the control logic 10 and the physical interface unit 14 communicate with each other by means of a transmit enable signal TXEN and a receive enable signal RXEN thereby transferring data over data bus 11. The physical interface unit 14 can notify the control logic 10 via a collision signal COL, that a collision has been detected when two network nodes try to transmit at the same time. With control signals 16, the control logic 10 reads or writes the buffering arrangement 12 through an address/data bus 18. The control logic 10 may also access the local bus 100 via bus interface signals 102. However, the store and forward limitation of such design requires the control logic 10 to ensure that the buffering arrangement 12 completes data transfer within a period called inter-frame gap, otherwise the communication system cannot support fast back-to-back transaction.
Traditional communication systems utilize a high speed single-port static random access memory (SRAM) or a dual-port SRAM as the buffering arrangement 12 to overcome the limitation. Nevertheless, it is difficult to handle the synchronicity problem between the local bus 100 and the physical interface unit 14 if the high speed single-port SRAM in a time-sharing manner is adopted to serve as the buffering arrangement 12. In a general dual-port SRAM, if data is to be read from and written to a single memory cell (or the same address), both the read and write operations are conducted concurrently as in the case of different addresses. Although a dual-port SRAM has two access ports so that more than one system unit may directly access the memory, the layout size of such a dual-port memory cell is approximately 5˜6 times the size of a single-port cell constructed using the same fabrication technology. This results in a larger chip area and, unfortunately, the cost of an integrated circuit goes up as its chip area is increased.
Accordingly, what is needed is a novel scheme for buffering data in a communication system, unencumbered by the limitations associated with the prior art.